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January 2007
HYS72D64301[G/H]BR-[5/6]-B HYS72D128xxx[G/H]BR-[5/6/7]-B HYS72D256220[G/H]BR-[5/6/7]-B HYS72D256320[G/H]BR-[5/6/7]-B
1 8 4 - P i n R e g i s t e r e d D o u bl e - D a t a - R a t e S D R A M M o d u l e DDR SDRAM RoHS Compliant Products
Internet Data Sheet
Rev. 1.42
Internet Data Sheet
HYS72D[64/128/256]xxx[G/H]BR-[5/6/7]-B Registered DDR SDRAM Module
HYS72D64301[G/H]BR-[5/6]-B, HYS72D128xxx[G/H]BR-[5/6/7]-B, HYS72D256220[G/H]BR-[5/6/7]-B, HYS72D256320[G/H]BR-[5/6/7]-B Revision History: 2007-01, Rev. 1.42 All All 67 Qimonda update Adapted internet edition Editorial Change
Previous Revision: 2006-03, Rev. 1.41 Previous Revision: 2004-05, Rev. 1.4
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qag_techdoc_rev400 / 3.2 QAG / 2006-07-21 03292006-7CZA-YS85
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Internet Data Sheet
HYS72D[64/128/256]xxx[G/H]BR-[5/6/7]-B Registered DDR SDRAM Module
1
1.1
Overview
Features
* 184-Pin Registered 8-Byte Dual-In-Line DDR SDRAM Module for "1U" PC, Workstation and Server main memory applications * One rank 128M x 72 and 64M x 72 organization, and two ranks 256M x 72 organization * Standard Double-Data-Rate Synchronous DRAMs (DDR SDRAM) with a single + 2.5 V ( 0.2 V) power supply and +2.6 V ( 0.1 V) power supply for DDR400 * Built with DDR SDRAMs in P-TFBGA-60 package * Programmable CAS Latency, Burst Length, and Wrap Sequence (Sequential & Interleave) * Auto Refresh (CBR) and Self Refresh * All inputs and outputs SSTL_2 compatible * RAS-lockout supported tRAP=tRCD * Re-drive for all input signals using register and PLL devices. * Serial Presence Detect with E2PROM * Low Profile Modules form factor: 133.35 mm x 28.58 mm (1.1") x 4.00 mm and 133.35 mm x 30.48 mm (1.2") x 4.00 mm * Standard reference card layout Raw Card "A", "B", "C", "D". * Gold plated contacts
TABLE 1
Performance
Part Number Speed Code Speed Grade max. Clock Frequency Component Module @CL3 @CL2.5 @CL2 -5 DDR400B PC3200-3033 -6 DDR333B PC2700-2533 166 166 133 -7 DDR266A PC2100-2033 -- 143 133 Unit -- -- MHz MHz MHz
fCK3 fCK2.5 fCK2
200 166 133
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Internet Data Sheet
HYS72D[64/128/256]xxx[G/H]BR-[5/6/7]-B Registered DDR SDRAM Module
1.2
Description
The HYS72D[64/128/256]xxx[G/H]BR-[5/6/7]-B are low profile versions of the standard Registered DIMM modules with 1.1" inch (28.58) and 1.2" inch (30,40 mm) height for 1U Server Applications. The Low Profile DIMM versions are available as 64M x 72(512 MB), 128M x 72 (1 GB) and 256M x 72 (2 GB). The memory array is designed with Double Data Rate Synchronous DRAMs for ECC applications. All control and address signals are re-driven on the DIMM using register devices and a PLL for the clock distribution. This reduces capacitive loading to the system bus, but adds one cycle to the SDRAM timing. A variety of de coupling capacitors are mounted on the PC board. The DIMMs feature serial presence detect based on a serial E2PROM device using the 2-pin I2C protocol. The first 128 bytes are programmed with configuration data and the second 128 bytes are available to the customer.
TABLE 2
Ordering Information for Lead - Containing Products
Product Type1) PC3200 (CL=3) HYS72D64301GBR-5-B HYS72D128300GBR-5-B HYS72D128321GBR-5-B HYS72D256220GBR-5-B PC2700 (CL=2.5) HYS72D64301GBR-6-B HYS72D128300GBR-6-B HYS72D128321GBR-6-B HYS72D256320GBR-6-B HYS72D256220GBR-6-B PC2100 (CL=2) HYS72D128300GBR-7-B HYS72D128321GBR-7-B HYS72D256220GBR-7-B HYS72D256320GBR-7-B PC2100R-20330-C0 PC2100R-20330-B0 PC2100R-20330-D0 PC2100R-20330-D0 one rank 1 GByte Reg. ECC DIMM two ranks1 GByte Reg. ECC DIMM two ranks 2 GByte Reg. ECC DIMM two ranks 2 GByte Reg. ECC DIMM 512 MBit (x4) 512 MBit (x8) 512 MBit (x4) 512 MBit (x4) PC2700R-25330-A0 PC2700R-25330-C0 PC2700R-25330-B0 PC2700R-25330-D0 PC2700R-25330-D0 one rank 512 MByte Reg. ECC DIMM one rank 1 GByte Reg. ECC DIMM two ranks 1 GByte Reg. ECC DIMM two ranks 2 GByte Reg. ECC DIMM two ranks 2 GByte Reg. ECC DIMM 512 MBit (x4) 512 MBit (x4) 512 MBit (x8) 512 MBit (x4) 512 MBit (x4) PC2700R-30331-A0 PC3200R-30331-C0 PC3200R-30331-B0 PC3200R-30331-D0 one rank 512 MByte Reg. ECC DIMM one rank 1 GByte Reg. ECC DIMM two ranks 1 GByte Reg. ECC DIMM two ranks 2 GByte Reg. ECC DIMM 512 MBit (x8) 512 MBit (x4) 512 MBit (x8) 512 MBit (x4) Compliance Code2) Description SDRAM Technology
1) All product types end with a place code designating the silicon-die revision. Reference information available on request. Example: HYS72D128300GBR-5-B, indicating Rev.B die are used for SDRAM components. 2) The Compliance Code is printed on the module labels and describes the speed sort (for example "PC2100R"), the latencies (for example "20330" means CAS latency of 2.0 clocks, Row-Column-Delay (RCD) latency of 3 clocks and Row Pre-charge latency of 3 clocks), JEDEC SPD code definition version 0, and the Raw Card used for this module.
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Internet Data Sheet
HYS72D[64/128/256]xxx[G/H]BR-[5/6/7]-B Registered DDR SDRAM Module
TABLE 3
Ordering information for Lead - Free (RoHS Complaint) Products
Product Type
1)2)
Compliance Code3)
Description
SDRAM Technology 512 MBit (x8) 512 MBit (x4) 512 MBit (x8) 512 MBit (x4) 512 MBit (x4) 512 MBit (x8) 512 MBit (x4) 512 MBit (x8) 512 MBit (x4) 512 MBit (x4) 512 MBit (x4) 512 MBit (x8) 512 MBit (x4) 512 MBit (x4)
PC3200 (CL=3) HYS72D64301HBR-5-B HYS72D128300HBR-5-B HYS72D128321HBR-5-B HYS72D256220HBR-5-B HYS72D256320HBR-5-B PC2700 (CL=2.5) HYS72D64301HBR-6-B HYS72D128300HBR-6-B HYS72D128321HBR-6-B HYS72D256220HBR-6-B HYS72D256320HBR-6-B PC2100 (CL=2) HYS72D128300HBR-7-B HYS72D128321HBR-7-B HYS72D256220HBR-7-B HYS72D256320HBR-7-B PC2100R-20330-C0 PC2100R-20330-B0 PC2100R-20330-D0 PC2100R-20330-F0 one rank 1 GByte Reg. ECC DIMM two ranks 1 GByte Reg. ECC DIMM two ranks 2 GByte Reg. ECC DIMM two ranks 2 GByte Reg. ECC DIMM PC2700R-25330-A0 PC2700R-25330-C0 PC2700R-25330-B0 PC2700R-25330-D0 PC2700R-25330-F0 one rank 512 MByte Reg. ECC DIMM one rank 1 GByte Reg. ECC DIMM two ranks 1 GByte Reg. ECC DIMM two ranks 2 GByte Reg. ECC DIMM two ranks 2 GByte Reg. ECC DIMM PC3200R-30331-A0 PC3200R-30331-C0 PC3200R-30331-B0 PC3200R-30331-D0 PC3200R-30331-F0 one rank 512 MByte Reg. ECC DIMM one rank 1 GByte Reg. ECC DIMM two ranks 1 GByte Reg. ECC DIMM two ranks 2 GByte Reg. ECC DIMM two ranks 2 GByte Reg. ECC DIMM
1) RoHS Compliant Product: Restriction of the use of certain hazardous substances (RoHS) in electrical and electronic equipment as defined in the directive 2002/95/EC issued by the European Parliament and of the Council of 27 January 2003. These substances include mercury, lead, cadmium, hexavalent chromium, polybrominated biphenyls and polybrominated biphenyl ethers. 2) All product types end with a place code designating the silicon-die revision. Reference information available on request. Example: HYS72D128300GBR-5-B, indicating Rev.B die are used for SDRAM components. 3) The Compliance Code is printed on the module labels and describes the speed sort (for example "PC2100R"), the latencies (for example "20330" means CAS latency of 2.0 clocks, Row-Column-Delay (RCD) latency of 3 clocks and Row Pre-charge latency of 3 clocks), JEDEC SPD code definition version 0, and the Raw Card used for this module.
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Internet Data Sheet
HYS72D[64/128/256]xxx[G/H]BR-[5/6/7]-B Registered DDR SDRAM Module
2
Pin Configuration
and Table 6 respectively. The pin numbering is depicted in Figure 1.
The pin configuration of the Registered DDR SDRAM DIMM is listed by function in Table 4 (184 pins). The abbreviations used in columns Pin and Buffer Type are explained in Table 5
TABLE 4
Pin Configuration of RDIMM
Pin# Name Pin Type I I I I NC I I NC I I I I Buffer Type SSTL SSTL SSTL SSTL SSTL SSTL SSTL -- SSTL SSTL SSTL LVCMOS SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL Address Bus 11:0 Function
Clock Signals 137 138 21 111 CK0 CK0 CKE0 CKE1 NC Control Signals 157 158 S0 S1 NC 154 65 63 10 RAS CAS WE RESET Chip Select of Rank 0 Chip Select of Rank 1 Note: 2-ranks module Note: 1-rank module Row Address Strobe Column Address Strobe Write Enable Register Reset Clock Signal Complement Clock Clock Enable Rank 0 Clock Enable Rank 1 Note: 2-rank module Note: 1-rank module
Address Signals 59 52 48 43 41 130 37 32 BA0 BA1 A0 A1 A2 A3 A4 A5 I I I I I I I I Bank Address Bus 1:0
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Internet Data Sheet
HYS72D[64/128/256]xxx[G/H]BR-[5/6/7]-B Registered DDR SDRAM Module
Pin# 125 29 122 27 141 118 115
Name A6 A7 A8 A9 A10 AP A11 A12 NC
Pin Type I I I I I I I I NC I NC I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O
Buffer Type SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL -- SSTL -- SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL
Function Address Bus 11:0
Address Signal 12 Note: Module based on 256 Mbit or larger dies Note: 128 Mbit based module Address Signal 13 Note: 1 Gbit based module Note: Module based on 512 Mbit or smaller dies Data Bus 63:0
167
A13 NC
Data Signals 2 4 6 8 94 95 98 99 12 13 19 20 105 106 109 110 23 24 28 31 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ16 DQ17 DQ18 DQ19
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HYS72D[64/128/256]xxx[G/H]BR-[5/6/7]-B Registered DDR SDRAM Module
Pin# 114 117 121 123 33 35 39 40 126 127 131 133 53 55 57 60 146 147 150 151 61 64 68 69 153 155 161 162 72 73 79 80 165 166 170 171 83 84 87 88
Name DQ20 DQ21 DQ22 DQ23 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DQ56 DQ57 DQ58 DQ59
Pin Type I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O
Buffer Type SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL
Function Data Bus 63:0
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HYS72D[64/128/256]xxx[G/H]BR-[5/6/7]-B Registered DDR SDRAM Module
Pin# 174 175 178 179 44 45 49 51 134 135 142 144 5 14 25 36 56 67 78 86 47 97
Name DQ60 DQ61 DQ62 DQ63 CB0 CB1 CB2 CB3 CB4 CB5 CB6 CB7 DQS0 DQS1 DQS2 DQS3 DQS4 DQS5 DQS6 DQS7 DQS8 DM0 DQS9
Pin Type I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I I/O I I/O I I/O I I/O I I/O
Buffer Type SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL
Function Data Bus 63:0
Check Bits 7:0
Data Strobes 8:0
Data Strobes 8:0
Data Mask 0 Note: x8 based module Data Strobe 9 Note: x4 based module Data Mask 1 Note: x8 based module Data Strobe 10 Note: x4 based module Data Mask 2 Note: x8 based module Data Strobe 11 Note: x4 based module Data Mask 3 Note: x8 based module Data Strobe 12 Note: x4 based module Data Mask 4 Note: x8 based module Data Strobe 13 Note: x4 based module
107
DM1 DQS10
119
DM2 DQS11
129
DM3 DQS12
149
DM4 DQS13
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Internet Data Sheet
HYS72D[64/128/256]xxx[G/H]BR-[5/6/7]-B Registered DDR SDRAM Module
Pin# 159 Name DM5 DQS14 169 DM6 DQS15 177 DM7 DQS16 140 DM8 DQS17 EEPROM 92 91 181 182 183 1 SCL SDA SA0 SA1 SA2 I I/O I I I AI PWR PWR CMOS OD CMOS CMOS CMOS -- -- -- I/O Reference Voltage EEPROM Power Supply I/O Driver Power Supply Serial Bus Clock Serial Bus Data Slave Address Select Bus 2:0 Pin Type I I/O I I/O I I/O I I/O Buffer Type SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL Function Data Mask 5 Note: x8 based module Data Strobe 14 Note: x4 based module Data Mask 6 Note: x8 based module Data Strobe 15 Note: x4 based module Data Mask 7 Note: x8 based module Data Strobe 16 Note: x4 based module Data Mask 8 Note: x8 based module Data Strobe 17 Note: x4 based module
Power Supplies
VREF 184 VDDSPD 15, 22, 30, VDDQ
54, 62, 77, 96, 104, 112, 128, 136, 143, 156, 164, 172, 180 7, 38, 46, 70, 85, 108, 120, 148, 168
VDD
PWR
--
Power Supply
3, 11, 18, VSS 26, 34, 42, 50, 58, 66, 74, 81, 89, 93, 100, 116, 124, 132, 139, 145, 152, 160, 176
GND
--
Ground Plane
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HYS72D[64/128/256]xxx[G/H]BR-[5/6/7]-B Registered DDR SDRAM Module
Pin# Other Pins 82
Name
Pin Type O NC
Buffer Type OD --
Function
VDDID
VDD Identification
Not connected
NC 9, 16, 17, 71, 75, 76, 90, 101, 102, 103, 113, 163, 173
TABLE 5
Abbrevations for Pin Type
Abbreviation I O I/O AI PWR GND NU NC Description Standard input-only pin. Digital levels. Output. Digital levels. I/O is a bidirectional input/output signal. Input. Analog levels. Power Ground Not Usable (JEDEC Standard) Not Connected (JEDEC Standard)
TABLE 6
Abbrevations for Buffer Type
Abbreviation SSTL LV-CMOS CMOS OD Description Serial Stub Terminalted Logic (SSTL2) Low Voltage CMOS CMOS Levels Open Drain. The corresponding pin has 2 operational states, active low and tristate, and allows multiple devices to share as a wire-OR.
TABLE 7
Address Format
Density 512 MB 1 GB 1 GB 2 GB Organization 64M x 72 128M x72 128M x72 256M x72 Memory Ranks 1 1 2 2 SDRAMs 64M x8 128M x4 64M x8 128M x4 # of SDRAMs 8 18 18 36 # of row/bank/ column bits 13/2/11 13/2/12 13/2/11 13/2/12 Refresh 8K 8K 8K 8K Period 64 ms 64 ms 64 ms 64 ms Interval 7.8 s 7.8 s 7.8 s 7.8 s
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Internet Data Sheet
HYS72D[64/128/256]xxx[G/H]BR-[5/6/7]-B Registered DDR SDRAM Module
FIGURE 1
Pin Configuration 184 Pins, Reg
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HYS72D[64/128/256]xxx[G/H]BR-[5/6/7]-B Registered DDR SDRAM Module
3
3.1
Electrical Characteristics
Operating Conditions
TABLE 8
Absolute Maximum Ratings
Parameter Symbol Min. Voltage on I/O pins relative to VSS Voltage on inputs relative to VSS Voltage on VDD supply relative to VSS Voltage on VDDQ supply relative to VSS Operating temperature (ambient) Storage temperature (plastic) Power dissipation (per SDRAM component) Short circuit output current Values Typ. -- -- -- -- -- -- 1 50 Max. Unit Note/ Test Condition -- -- -- -- -- -- -- --
VIN, VOUT VIN VDD VDDQ TA TSTG PD IOUT
-0.5 -1 -1 -1 0 -55 -- --
VDDQ + 0.5
+3.6 +3.6 +3.6 +70 +150 -- --
V V V V C C W mA
Attention: Permanent damage to the device may occur if "Absolute Maximum Ratings" are exceeded. This is a stress rating only, and functional operation should be restricted to recommended operation conditions. Exposure to absolute maximum rating conditions for extended periods of time may affect device reliability and exceeding only one of the values may cause irreversible damage to the integrated circuit.
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HYS72D[64/128/256]xxx[G/H]BR-[5/6/7]-B Registered DDR SDRAM Module
TABLE 9
Electrical Characteristics and DC Operating Conditions
Parameter Symbol Min. Device Supply Voltage Device Supply Voltage Output Supply Voltage Output Supply Voltage Supply Voltage, I/O Supply Voltage Input Reference Voltage I/O Termination Voltage (System) Input High (Logic1) Voltage Values Typ. 2.5 2.6 2.5 2.6 -- 0.5 x VDDQ -- -- -- -- -- -- -- -- -- Max. 2.7 2.7 2.7 2.7 0 0.51 x VDDQ V V V V V V V V V V V -- A A mA mA Unit Note/Test Condition1)
VDD VDD VDDQ VDDQ VSS, VSSQ VREF VTT
2.3 2.5 2.3 2.5 0 0.49 x VDDQ
fCK 166 MHz fCK > 166 MHz 2) fCK 166 MHz 3) fCK > 166 MHz 2)3)
--
4) 5)
VREF - 0.04 VREF + 0.15
-0.3 -0.3 0.36 0.71 -2 -5 --
VREF + 0.04 VDDQ + 0.3 VREF - 0.15 VDDQ + 0.3 VDDQ + 0.6
1.4 2 5 -16.2 --
VIH(DC) Input Low (Logic0) Voltage VIL(DC) Input Voltage Level, CK and VIN(DC)
CK Inputs Input Differential Voltage, CK and CK Inputs VI-Matching Pull-up Current to Pull-down Current Input Leakage Current Output Leakage Current
6) 6) 6)
VID(DC) VIRatio II IOZ
6)7)
8)
Any input 0 V VIN VDD; All other pins not under test = 0 V9) DQs are disabled; 0 V VOUT
Output High Current, Normal IOH Strength Driver
VDDQ 9) VOUT = 1.95 V VOUT = 0.35 V
16.2 -- Output Low Current, Normal IOL Strength Driver 1) 0 C TA 70 C; VDDQ = 2.5 V 0.2 V, VDD = +2.5 V 0.2 V;
2) 3) 4) 5) 6) 7) 8)
9)
DDR400 conditions apply for all clock frequencies above 166 MHz Under all conditions, VDDQ must be less than or equal to VDD. Peak to peak AC noise on VREF may not exceed 2 % VREF.DC. VREF is also expected to track noise variations in VDDQ. VTT is not applied directly to the device. VTT is a system supply for signal termination resistors, is expected to be set equal to VREF, and must track variations in the DC level of VREF. Inputs are not recognized as valid until VREF stabilizes. VID is the magnitude of the difference between the input level on CK and the input level on CK. The ratio of the pull-up current to the pull-down current is specified for the same temperature and voltage, over the entire temperature and voltage range, for device drain to source voltage from 0.25 to 1.0 V. For a given output, it represents the maximum difference between pull-up and pull-down drivers due to process variation. Values are shown per pin.
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HYS72D[64/128/256]xxx[G/H]BR-[5/6/7]-B Registered DDR SDRAM Module
TABLE 10
IDD Conditions
Parameter Operating Current 0 one bank; active/ precharge; DQ, DM, and DQS inputs changing once per clock cycle; address and control inputs changing once every two clock cycles. Operating Current 1 one bank; active/read/precharge; Burst Length = 4; see component data sheet. Precharge Power-Down Standby Current all banks idle; power-down mode; CKE VIL,MAX Precharge Floating Standby Current CS VIH,,MIN, all banks idle; CKE VIH,MIN; address and other control inputs changing once per clock cycle; VIN = VREF for DQ, DQS and DM. Precharge Quiet Standby Current CS VIHMIN, all banks idle; CKE VIH,MIN; VIN = VREF for DQ, DQS and DM; address and other control inputs stable at VIH,MIN or VIL,MAX. Active Power-Down Standby Current one bank active; power-down mode; CKE VILMAX; VIN = VREF for DQ, DQS and DM. Active Standby Current one bank active; CS VIH,MIN; CKE VIH,MIN; tRC = tRAS,MAX; DQ, DM and DQS inputs changing twice per clock cycle; address and control inputs changing once per clock cycle. Operating Current Read one bank active; Burst Length = 2; reads; continuous burst; address and control inputs changing once per clock cycle; 50 % of data outputs changing on every clock edge; CL = 2 for DDR266(A), CL = 3 for DDR333 and DDR400B; IOUT = 0 mA Operating Current Write one bank active; Burst Length = 2; writes; continuous burst; address and control inputs changing once per clock cycle; 50 % of data outputs changing on every clock edge; CL = 2 for DDR266(A), CL = 3 for DDR333 and DDR400B Auto-Refresh Current tRC = tRFCMIN, burst refresh Self-Refresh Current CKE 0.2 V; external clock on Operating Current 7 four bank interleaving with Burst Length = 4; see component data sheet. Symbol
IDD0
IDD1 IDD2P IDD2F
IDD2Q
IDD3P IDD3N
IDD4R
IDD4W
IDD5 IDD6 IDD7
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HYS72D[64/128/256]xxx[G/H]BR-[5/6/7]-B Registered DDR SDRAM Module
TABLE 11
IDD Specification for HYS72D[64/128/256]xxx[G/H]BR-5-B
HYS72D128300GBR-5-B HYS72D128300HBR-5-B HYS72D128321GBR-5-B HYS72D128321HBR-5-B HYS72D64301GBR-5-B HYS72D64301HBR-5-B Product Type HYS72D256220GBR-5-B HYS72D256220HBR-5-B HYS72D256320HBR-5-B Unit Note/ Test Conditions1) 2)
Organization
512 MB x72 1 Rank -5
1 GB x72 1 Rank -5 Max. 1460 1690 430 990 630 540 1090 1600 1650 2620 390 3190 Typ. 2250 2560 690 1450 1000 870 1610 2470 2560 4360 660 Max. 2660 2980 770 1620 1160 980 1820 2800 2890 5120 740
1 GB x72 2 Ranks -5 Typ. 1880 2100 690 1450 1000 870 1610 2050 2100 2870 660 Max. 2180 2410 770 1620 1160 980 1820 2320 2370 3340 740
2 GB x72 2 Ranks -5 Typ. 3550 3860 1320 2590 1940 1690 2910 3770 3860 5660 1310 Max. 4110 4430 1440 2870 2230 1870 3260 4250 4340 6570 1430 mA mA mA mA mA mA mA mA mA mA mA
3) 3)4) 5) 5) 5) 5) 5) 3)4) 3) 3) 5)
Symbol
Typ. 1230 1450 410 880 530 460 960 1400 1450 2210 360 2700
IDD0 IDD1 IDD2P IDD2F IDD2Q IDD3P IDD3N IDD4R IDD4W IDD5 IDD6 IDD7
1) 2) 3)
4) 5)
3)4) 5620 6580 3630 4210 6920 8030 mA Test condition for maximum values: VDD = 2.7 V, TA = 10 C Module IDD is calculated on the basis of component IDD and includes Register and PLL currents The module IDD values are calculated from the component IDD data sheet values are: n * IDDx[component] for single bank modules (n: number of components per module bank) n * IDDx[component] + n * IDD3N[component] for two bank modules (n: number of components per module bank) DQ I/O (IDDQ) currents are not included into calculations: module IDD values will be measured differently depending on load conditions The module IDD values are calculated from the component IDD decathlete values are: n * IDDx[component] for single bank modules (n: number of components per module bank) 2 * n * IDDx[component] for single two bank modules (n: number of components per module bank)
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HYS72D[64/128/256]xxx[G/H]BR-[5/6/7]-B Registered DDR SDRAM Module
TABLE 12
IDD Specification for HYS72D[64/128/256]xxx[G/H]BR-6-B
HYS72D128300GBR-6-B HYS72D128300HBR-6-B HYS72D128321GBR-6-B HYS72D128321HBR-6-B HYS72D64301GBR-6-B HYS72D64301HBR-6-B Product Type HYS72D256220GBR-6-B HYS72D256320GBR-6-B HYS72D256220HBR-6-B HYS72D256320HBR-6-B Unit Note/ Test Conditions1) 2)
Organization
512 MB x72 1 Rank -6
1 GB x72 1 Rank -6 Max. 1320 1540 400 880 580 500 980 1450 1500 2360 390 2880 Typ. 2060 2360 610 1250 890 780 1430 2210 2290 3920 600 Max. 2380 2690 690 1400 1050 890 1600 2510 2600 4590 680
1 GB x72 2 Ranks -6 Typ. 1700 1910 610 1250 890 780 1430 1840 1870 2570 600 Max. 1940 2160 690 1400 1050 890 1600 2070 2110 2970 680
2 GB x72 2 Ranks -6 Typ. 3190 3490 1140 2200 1690 1480 2560 3340 3420 5050 1150 Max. 3620 3930 1260 2440 1980 1660 2840 3750 3840 5820 1270 mA mA mA mA mA mA mA mA mA mA mA
3) 3)4) 5) 5) 5) 5) 5) 3)4) 3) 3) 5)
Symbol
Typ. 1130 1340 380 780 480 430 870 1270 1310 2010 350 2440
IDD0 IDD1 IDD2P IDD2F IDD2Q IDD3P IDD3N IDD4R IDD4W IDD5 IDD6 IDD7
1) 2) 3)
4) 5)
3)4) 5040 5910 3250 3770 6170 7150 mA Test condition for maximum values: VDD = 2.7 V, TA = 10 C Module IDD is calculated on the basis of component IDD and includes Register and PLL currents The module IDD values are calculated from the component IDD decathlete values are: n * IDDx[component] for single bank modules (n: number of components per module bank) n * IDDx[component] + n * IDD3N[component] for two bank modules (n: number of components per module bank) DQ I/O (IDDQ) currents are not included into calculations: module IDD values will be measured differently depending on load conditions The module IDD values are calculated from the component IDD decathlete values are: n * IDDx[component] for single bank modules (n: number of components per module bank) 2 * n * IDDx[component] for single two bank modules (n: number of components per module bank)
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Internet Data Sheet
HYS72D[64/128/256]xxx[G/H]BR-[5/6/7]-B Registered DDR SDRAM Module
TABLE 13
IDD Specification for HYS72D[128/256]xxx[G/H]BR-7-B
HYS72D128300GBR-7-B HYS72D128300HBR-7-B HYS72D128321GBR-7-B HYS72D128321HBR-7-B Product Type HYS72D256220GBR-7-B HYS72D256320GBR-7-B HYS72D256220HBR-7-B HYS72D256320HBR-7-B Unit Note/ Test Conditions1) 2)
Organization
1 GB x72 1 Rank -7
1 GB x72 2 Ranks -7 Max. 2060 2390 610 1180 910 770 1380 2170 2260 4230 620 Typ. 1460 1650 530 1050 770 660 1210 1580 1620 2300 540 Max. 1670 1900 610 1180 910 770 1380 1790 1830 2700 620
2 GB x72 2 Ranks -7 Typ. 2700 2990 960 1810 1440 1230 2140 2840 2920 4490 990 Max. 3090 3420 1080 2010 1690 1400 2410 3200 3290 5260 1110 mA mA mA mA mA mA mA mA mA mA mA
3) 3)4) 5) 5) 5) 5) 5) 3)4) 3) 3) 5)
Symbol
Typ. 1780 2070 530 1050 770 660 1210 1920 1990 3570 540 4390
IDD0 IDD1 IDD2P IDD2F IDD2Q IDD3P IDD3N IDD4R IDD4W IDD5 IDD6 IDD7
1) 2) 3)
4) 5)
3)4) 5140 2810 3270 5310 6170 mA Test condition for maximum values: VDD = 2.7 V, TA = 10 C Module IDD is calculated on the basis of component IDD and includes Register an PLL The module IDD values are calculated from the component IDD decathlete values are: n * IDDx[component] for single bank modules (n: number of components per module bank) n * IDDx[component] + n * IDD3N[component] for two bank modules (n: number of components per module bank) DQ I/O (IDDQ) currents are not included into calculations: module IDD values will be measured differently depending on load conditions The module IDD values are calculated from the component IDD decathlete values are: n * IDDx[component] for single bank modules (n: number of components per module bank) 2 * n * IDDx[component] for single two bank modules (n: number of components per module bank)
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Internet Data Sheet
HYS72D[64/128/256]xxx[G/H]BR-[5/6/7]-B Registered DDR SDRAM Module
TABLE 14
AC Timing - Absolute Specifications for PC3200 and PC2700
Parameter Symbol -5 DDR400B Min. DQ output access time from CK/CK CK high-level width Clock cycle time Max. +0.5 0.55 8 12 12 0.55 -6 DDR333 Min. -0.7 0.45 6 6 7.5 0.45 Max. +0.7 0.55 12 12 12 0.55 ns
2)3)4)5)
Unit Note/ Test Condition1)
tAC tCH tCK
-0.5 0.45 5 6 7.5
tCK
ns ns ns
2)3)4)5)
CL = 3.0 2)3)4)5) CL = 2.5 2)3)4)5) CL = 2.0 2)3)4)5)
2)3)4)5) 2)3)4)5)6)
CK low-level width Auto precharge write recovery + precharge time DQ and DM input hold time DQ and DM input pulse width (each input) DQS output access time from CK/CK DQS input low (high) pulse width (write cycle) DQS-DQ skew (DQS and associated DQ signals) Write command to 1 DQS latching transition DQ and DM input setup time DQS falling edge hold time from CK (write cycle)
st
tCL tDAL tDH tDIPW tDQSCK tDQSL,H tDQSQ tDQSS tDS tDSH
0.45 (tWR/tCK)+(tRP/tCK) 0.4 1.75 -0.6 0.35 -- 0.72 0.4 0.2 0.2 Min. (tCL, tCH) -- 0.6 0.7
tCK tCK
ns ns ns
-- -- +0.6 -- +0.40 1.25 -- -- -- -- +0.7 -- -- -- -- --
0.45 1.75 -0.6 0.35 -- 0.75 0.45 0.2 0.2 Min. (tCL, tCH) -- 0.75 0.8 2.2 0.75 0.8
-- -- +0.6 -- +0.40 1.25 -- -- -- -- +0.7 -- -- -- -- --
2)3)4)5) 2)3)4)5)6)
2)3)4)5)
tCK
ns
2)3)4)5)
TFBGA
2)3)4)5) 2)3)4)5)
tCK
ns
2)3)4)5) 2)3)4)5)
tCK tCK
ns ns ns ns ns ns ns
DQS falling edge to CK setup time tDSS (write cycle) Clock Half Period Data-out high-impedance time from CK/CK Address and control input hold time
2)3)4)5)
tHP tHZ tIH
2)3)4)5) 2)3)4)5)7)
Fast slew rate
3)4)5)6)8)
Slow slew rate3)4)5)6)8)
2)3)4)5)9)
Control and Addr. input pulse width (each input) Address and control input setup time
tIPW tIS
2.2 0.6 0.7
Fast slew rate
3)4)5)6)8)
Slow slew rate3)4)5)6)8)
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Internet Data Sheet
HYS72D[64/128/256]xxx[G/H]BR-[5/6/7]-B Registered DDR SDRAM Module
Parameter
Symbol
-5 DDR400B Min. Max. +0.7 -- -- +0.50 -- 70E+3 -- -- 7.8 -- -- 1.1 0.60 -- -- -- 0.60 -- -- --
-6 DDR333 Min. -0.7 2 Max. +0.7 -- -- +0.50 -- 70E+3 -- -- 7.8 -- -- 1.1 0.60 -- -- -- 0.60 -- -- --
Unit Note/ Test Condition1)
Data-out low-impedance time from CK/CK
tLZ
-0.7 2
ns
2)3)4)5)7)
Mode register set command cycle tMRD time DQ/DQS output hold time from DQS Data hold skew factor Active to Autoprecharge delay Active to Precharge command Active to Active/Auto-refresh command period Active to Read or Write delay
tCK
ns ns ns ns ns ns s ns ns
2)3)4)5)
tQH tQHS tRAP tRAS tRC
tHP -tQHS
--
tHP -tQHS
--
2)3)4)5)
TFBGA 2)3)4)5)
2)3)4)5) 2)3)4)5) 2)3)4)5)
tRCD
40 55 15 -- 65 15 0.9 0.40 10 0.25 0 0.40 15 2 75
tRCD
42 60 18 -- 72 18 0.9 0.40 12 0.25 0 0.40 15 1 75
tRCD Average Periodic Refresh Interval tREFI Auto-refresh to Active/AutotRFC
refresh command period Read preamble Read postamble Active bank A to Active bank B command Write preamble Write preamble setup time Write postamble Write recovery time Internal write to read command delay Exit self-refresh to non-read command Precharge command period
2)3)4)5) 2)3)4)5)10) 2)3)4)5)
tRP tRPRE tRPST tRRD tWPRE tWPRES tWPST tWR tWTR tXSNR
2)3)4)5) 2)3)4)5) 2)3)4)5) 2)3)4)5)
tCK tCK
ns
tCK
ns
2)3)4)5) 2)3)4)5)11) 2)3)4)5)12) 2)3)4)5) 2)3)4)5)
tCK
ns
tCK
ns
2)3)4)5)
2) Input slew rate 1 V/ns for DDR400, DDR333 3) The CK/CK input reference level (for timing reference to CK/CK) is the point at which CK and CK cross: the input reference level for signals other than CK/CK, is VREF. CK/CK slew rate are 1.0 V/ns. 4) Inputs are not recognized as valid until VREF stabilizes. 5) The Output timing reference level, as measured at the timing reference point indicated in AC Characteristics (note 3) is VTT. 6) For each of the terms, if not already an integer, round to the next highest integer. tCK is equal to the actual system clock cycle time. 7) tHZHZ and tLZ transitions occur in the same access time windows as valid data transitions. These parameters are not referred to a specific voltage level, but specify when the device is no longer driving (HZ), or begins driving (LZ). 8) Fast slew rate 1.0 V/ns , slow slew rate 0.5 V/ns and < 1 V/ns for command/address and CK & CK slew rate > 1.0 V/ns, measured between VIH(ac) and VIL(ac). 9) These parameters guarantee device timing, but they are not necessarily tested on each device. 10) A maximum of eight Autorefresh commands can be posted to any given DDR SDRAM device.
2)3)4)5) Exit self-refresh to read command tXSRD 200 -- 200 -- tCK 1) 0 C TA 70 C; VDDQ = 2.5 V 0.2 V, VDD = +2.5 V 0.2 V (DDR333); VDDQ = 2.6 V 0.1 V, VDD = +2.6 V 0.1 V (DDR400)
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Internet Data Sheet
HYS72D[64/128/256]xxx[G/H]BR-[5/6/7]-B Registered DDR SDRAM Module
11) The specific requirement is that DQS be valid (HIGH,LOW, or some point on a valid transition) on or before this CK edge. A valid transition is defined as monotonic and meeting the input slew rate specificationsof the device. When no writes were previously in progress on the bus, DQS will be transitioning from Hi-Z to logic LOW. If a previous write was in progress, DQS could be HIGH, LOW at this time, depending on tDQSS. 12) The maximum limit for this parameter is not a device limit. The device operates with a greater value for this parameter, but system performance (bus turnaround) degrades accordingly.
TABLE 15
AC Timing - Absolute Specifications for PC2100
Parameter Symbol -7 DDR266A Min. DQ output access time from CK/CK CK high-level width Clock cycle time Max. +0.75 0.55 12 12 12 0.55 -- -- -- +0.75 -- +0.5 1.25 -- -- -- -- +0.75 -- -- -- -- -- +0.75 -- -- 0.75 ns
2)3)4)5) 2)3)4)5)
Unit
Note/Test Condition 1)
tAC tCH tCK
-0.75 0.45 7 7.5 7.5
tCK
-- ns ns
CL = 32)3)4)5) CL = 2.52)3)4)5) CL = 2.02)3)4)5)
2)3)4)5) 2)3)4)5)6) 2)3)4)5) 2)3)4)5)6) 2)3)4)5) 2)3)4)5)
CK low-level width Auto precharge write recovery + precharge time DQ and DM input hold time DQ and DM input pulse width (each input) DQS output access time from CK/CK DQS input low (high) pulse width (write cycle) DQS-DQ skew (DQS and associated DQ signals) Write command to 1st DQS latching transition DQ and DM input setup time DQS falling edge hold time from CK (write cycle) DQS falling edge to CK setup time (write cycle) Clock Half Period Data-out high-impedance time from CK/CK Address and control input hold time
tCL tDAL tDH tDIPW tDQSCK tDQSL,H tDQSQ tDQSS tDS tDSH tDSS tHP tHZ tIH
0.45 (tWR/tCK)+(tRP/tCK) 0.5 1.75 -0.75 0.35 -- 0.75 0.5 0.2 0.2 min. (tCL, tCH) -- 0.9 1.0
tCK tCK
ns ns ns
tCK
ns
FBGA2)3)4)5)
2)3)4)5) 2)3)4)5) 2)3)4)5) 2)3)4)5) 2)3)4)5) 2)3)4)5)7)
tCK
ns
tCK tCK
ns ns ns ns ns ns ns ns
fast slew rate
3)4)5)6)8)
slow slew rate
3)4)5)6)8) 2)3)4)5)9)
Control and Addr. input pulse width (each input) Address and control input setup time
tIPW tIS
2.2 0.9 1.0
fast slew rate
3)4)5)6)8)
slow slew rate
3)4)5)6)8) 2)3)4)5)7) 2)3)4)5) 2)3)4)5)
Data-out low-impedance time from CK/CK Mode register set command cycle time DQ/DQS output hold time from DQS Data hold skew factor
tLZ tMRD tQH tQHS
-0.75 2
tCK
ns ns
tHP - tQHS
--
FBGA2)3)4)5)
Rev. 1.42, 2007-01 03292006-7CZA-YS85
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Internet Data Sheet
HYS72D[64/128/256]xxx[G/H]BR-[5/6/7]-B Registered DDR SDRAM Module
Parameter
Symbol
-7 DDR266A Min. Max. -- 120E+3 -- -- -- -- -- 1.1 0.6 -- -- -- -- -- -- -- --
Unit
Note/Test Condition 1)
tRAP Active to Precharge command tRAS Active to Active/Auto-refresh command period tRC Active to Read or Write delay tRCD Average Periodic Refresh Interval tREFI Auto-refresh to Active/Auto-refresh command period tRFC Precharge command period tRP Read preamble tRPRE Read postamble tRPST Active bank A to Active bank B command tRRD Write preamble tWPRE Write preamble setup time tWPRES Write postamble tWPST Write recovery time tWR Internal write to read command delay tWTR Exit self-refresh to non-read command tXSNR Exit self-refresh to read command tXSRD
Active to Read w/AP delay
tRCD
45 65 20 7.8 75 20 0.9 0.4 15 0.25 0 0.4 15 1 75 200
ns ns ns ns s ns ns
2)3)4)5) 2)3)4)5) 2)3)4)5) 2)3)4)5) 2)3)4)5)10) 2)3)4)5) 2)3)4)5) 2)3)4)5) 2)3)4)5) 2)3)4)5) 2)3)4)5) 2)3)4)5)11) 2)3)4)5)12) 2)3)4)5) 2)3)4)5) 2)3)4)5)13) 2)3)4)5)
tCK tCK
ns
tCK
ns
tCK
ns
tCK
ns
tCK
1) VDDQ = 2.5 V 0.2 V, VDD = +2.5 V 0.2 V ; 0 C TA 70 C 2) Input slew rate 1 V/ns 3) The CK/CK input reference level (for timing reference to CK/CK) is the point at which CK and CK cross: the input reference level for signals other than CK/CK, is VREF. CK/CK slew rate are 1.0 V/ns. 4) Inputs are not recognized as valid until VREF stabilizes. 5) The Output timing reference level, as measured at the timing reference point indicated in AC Characteristics (note 3) is VTT. 6) For each of the terms, if not already an integer, round to the next highest integer. tCK is equal to the actual system clock cycle time. 7) tHZ and tLZ transitions occur in the same access time windows as valid data transitions. These parameters are not referred to a specific voltage level, but specify when the device is no longer driving (HZ), or begins driving (LZ). 8) Fast slew rate 1.0 V/ns , slow slew rate 0.5 V/ns and < 1 V/ns for command/address and CK & CK slew rate > 1.0 V/ns, measured between VIH(ac) and VIL(ac). 9) These parameters guarantee device timing, but they are not necessarily tested on each device. 10) A maximum of eight Autorefresh commands can be posted to any given DDR SDRAM device. 11) The specific requirement is that DQS be valid (HIGH, LOW, or some point on a valid transition) on or before this CK edge. A valid transition is defined as monotonic and meeting the input slew rate specifications of the device. When no writes were previously in progress on the bus, DQS will be transitioning from Hi-Z to logic LOW. If a previous write was in progress, DQS could be HIGH, LOW, or transitioning from HIGH to LOW at this time, depending on tDQSS. 12) The maximum limit for this parameter is not a device limit. The device operates with a greater value for this parameter, but system performance (bus turnaround) degrades accordingly. 13) In all circumstances, tXSNR can be satisfied using tXSNR = tRFC,min + 1 x tCK
Rev. 1.42, 2007-01 03292006-7CZA-YS85
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Internet Data Sheet
HYS72D[64/128/256]xxx[G/H]BR-[5/6/7]-B Registered DDR SDRAM Module
4
SPD Codes
This chapter lists all hexadecimal byte values stored in the EEPROM of the products described in this data sheet. SPD stands for serial presence detect. All values with XX in the table are module specific bytes which are defined during production. List of SPD Code Tables * * * * * * Table 16 "HYS72D[64/128/256]xxxGBR-5-B" on Page 23 Table 17 "HYS72D[64/128/256]xxxGBR-6-B" on Page 27 Table 18 "HYS72D[128/256]xxxGBR-7-B" on Page 31 Table 19 "HYS72D[128/256]xxxHBR-5-B" on Page 35 Table 20 "HYS72D[128/256]xxxHBR-6-B" on Page 39 Table 21 "HYS72D[128/256]xxxHBR-7-B" on Page 43
TABLE 16
HYS72D[64/128/256]xxxGBR-5-B
HYS72D128300GBR-5-B HYS72D128321GBR-5-B HYS72D64301GBR-5-B Product Type HYS72D256220GBR-5-B 2 GByte x72 PC3200R- 30331 Rev. 1.0 HEX 80 08 07 0D 0C 02 48 00 04 50
Organization
512MB x72 1 Rank (x8)
1 GByte x72 1 Rank (x4) PC3200R- 30331 Rev. 1.0 HEX 80 08 07 0D 0C 01 48 00 04 50
1 GByte x72
2 Ranks (x8) 2 Ranks (x4) PC3200R- 30331 Rev. 1.0 HEX 80 08 07 0D 0B 02 48 00 04 50
Label Code JEDEC SPD Revision Byte# 0 1 2 3 4 5 6 7 8 9 Description Programmed SPD Bytes in E2PROM Total number of Bytes in E2PROM Memory Type (DDR = 07h) Number of Row Addresses Number of Column Addresses Number of DIMM Ranks Data Width (LSB) Data Width (MSB) Interface Voltage Levels tCK @ CLmax (Byte 18) [ns]
PC3200R- 30331 Rev. 1.0 HEX 80 08 07 0D 0B 01 48 00 04 50
Rev. 1.42, 2007-01 03292006-7CZA-YS85
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Internet Data Sheet
HYS72D[64/128/256]xxx[G/H]BR-[5/6/7]-B Registered DDR SDRAM Module
HYS72D128300GBR-5-B
HYS72D128321GBR-5-B
Organization
512MB x72 1 Rank (x8)
HYS72D64301GBR-5-B
Product Type
1 GByte x72 1 Rank (x4) PC3200R- 30331 Rev. 1.0 HEX 50 02 82 04 04 01 0E 04 1C 01 02 26 C1 60 50 75 50 3C 28 3C 28 01 60 60 40
1 GByte x72
2 GByte x72
2 Ranks (x8) 2 Ranks (x4) PC3200R- 30331 Rev. 1.0 HEX 50 02 82 08 08 01 0E 04 1C 01 02 26 C1 60 50 75 50 3C 28 3C 28 80 60 60 40 PC3200R- 30331 Rev. 1.0 HEX 50 02 82 04 04 01 0E 04 1C 01 02 26 C1 60 50 75 50 3C 28 3C 28 01 60 60 40
Label Code JEDEC SPD Revision Byte# 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 Description tAC SDRAM @ CLmax (Byte 18) [ns] Error Correction Support Refresh Rate Primary SDRAM Width Error Checking SDRAM Width tCCD [cycles] Burst Length Supported Number of Banks on SDRAM Device CAS Latency CS Latency Write Latency DIMM Attributes Component Attributes tCK @ CLmax -0.5 (Byte 18) [ns] tAC SDRAM @ CLmax -0.5 [ns] tCK @ CLmax -1 (Byte 18) [ns] tAC SDRAM @ CLmax -1 [ns] tRPmin [ns] tRRDmin [ns] tRCDmin [ns] tRASmin [ns] Module Density per Rank tAS, tCS [ns] tAH, tCH [ns] tDS [ns]
PC3200R- 30331 Rev. 1.0 HEX 50 02 82 08 08 01 0E 04 1C 01 02 26 C1 60 50 75 50 3C 28 3C 28 80 60 60 40
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HYS72D256220GBR-5-B
Internet Data Sheet
HYS72D[64/128/256]xxx[G/H]BR-[5/6/7]-B Registered DDR SDRAM Module
HYS72D128300GBR-5-B
HYS72D128321GBR-5-B
Organization
512MB x72 1 Rank (x8)
HYS72D64301GBR-5-B
Product Type
1 GByte x72 1 Rank (x4) PC3200R- 30331 Rev. 1.0 HEX 40 00 37 41 28 28 50 00 01 00 10 E1 7F 7F 7F 7F 7F 51 00 00 xx 37 32 44 31
1 GByte x72
2 GByte x72
2 Ranks (x8) 2 Ranks (x4) PC3200R- 30331 Rev. 1.0 HEX 40 00 37 41 28 28 50 00 01 00 10 68 7F 7F 7F 7F 7F 51 00 00 xx 37 32 44 31 PC3200R- 30331 Rev. 1.0 HEX 40 00 37 41 28 28 50 00 01 00 10 E2 7F 7F 7F 7F 7F 51 00 00 xx 37 32 44 32
Label Code JEDEC SPD Revision Byte# 35 36 - 40 41 42 43 44 45 46 47 48 - 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 Description tDH [ns] Not used tRCmin [ns] tRFCmin [ns] tCKmax [ns] tDQSQmax [ns] tQHSmax [ns] not used DIMM PCB Height Not used SPD Revision Checksum of Byte 0-62 Manufacturer's JEDEC ID Code (1) Manufacturer's JEDEC ID Code (2) Manufacturer's JEDEC ID Code (3) Manufacturer's JEDEC ID Code (4) Manufacturer's JEDEC ID Code (5) Manufacturer's JEDEC ID Code (6) Manufacturer's JEDEC ID Code (7) Manufacturer's JEDEC ID Code (8) Module Manufacturer Location Part Number, Char 1 Part Number, Char 2 Part Number, Char 3 Part Number, Char 4
PC3200R- 30331 Rev. 1.0 HEX 40 00 37 41 28 28 50 00 01 00 10 67 7F 7F 7F 7F 7F 51 00 00 xx 37 32 44 36
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HYS72D256220GBR-5-B
Internet Data Sheet
HYS72D[64/128/256]xxx[G/H]BR-[5/6/7]-B Registered DDR SDRAM Module
HYS72D128300GBR-5-B
HYS72D128321GBR-5-B
Organization
512MB x72 1 Rank (x8)
HYS72D64301GBR-5-B
Product Type
1 GByte x72 1 Rank (x4) PC3200R- 30331 Rev. 1.0 HEX 32 38 33 30 30 47 42 52 35 42 20 20 20 20 1x xx xx xx xx 00
1 GByte x72
2 GByte x72
2 Ranks (x8) 2 Ranks (x4) PC3200R- 30331 Rev. 1.0 HEX 32 38 33 32 31 47 42 52 35 42 20 20 20 20 1x xx xx xx xx 00 PC3200R- 30331 Rev. 1.0 HEX 35 36 32 32 30 47 42 52 35 42 20 20 20 20 1x xx xx xx xx 00
Label Code JEDEC SPD Revision Byte# 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 - 98 Description Part Number, Char 5 Part Number, Char 6 Part Number, Char 7 Part Number, Char 8 Part Number, Char 9 Part Number, Char 10 Part Number, Char 11 Part Number, Char 12 Part Number, Char 13 Part Number, Char 14 Part Number, Char 15 Part Number, Char 16 Part Number, Char 17 Part Number, Char 18 Module Revision Code Test Program Revision Code Module Manufacturing Date Year Module Manufacturing Date Week Module Serial Number
PC3200R- 30331 Rev. 1.0 HEX 34 33 30 31 47 42 52 35 42 20 20 20 20 20 0x xx xx xx xx 00
99 - 127 Not used
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HYS72D256220GBR-5-B
Internet Data Sheet
HYS72D[64/128/256]xxx[G/H]BR-[5/6/7]-B Registered DDR SDRAM Module
TABLE 17
HYS72D[64/128/256]xxxGBR-6-B
HYS72D128300GBR-6-B HYS72D128321GBR-6-B HYS72D256320GBR-6-B HYS72D64301GBR-6-B Product Type HYS72D256220GBR-6-B 2 GByte x72 2 Ranks (x4) Rev. 1.0 HEX 80 08 07 0D 0C 02 48 00 04 60 70 02 82 04 04 01 0E 04 0C 01 02 26
Organization
512MB x72 1 Rank (x8)
1 GByte x72 1 Rank (x4)
1 GByte x72 2 Ranks (x8)
2 GByte x72 2 Ranks (x4)
Label Code JEDEC SPD Revision Byte# 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 Description Programmed SPD Bytes in E PROM Total number of Bytes in E PROM Memory Type (DDR = 07h) Number of Row Addresses Number of Column Addresses Number of DIMM Ranks Data Width (LSB) Data Width (MSB) Interface Voltage Levels tCK @ CLmax (Byte 18) [ns] tAC SDRAM @ CLmax (Byte 18) [ns] Error Correction Support Refresh Rate Primary SDRAM Width Error Checking SDRAM Width tCCD [cycles] Burst Length Supported Number of Banks on SDRAM Device CAS Latency CS Latency Write Latency DIMM Attributes
2 2
PC2700R PC2700R PC2700R PC2700R PC2700R -25331 -25330 -25330 -25330 -25331 Rev. 1.0 HEX 80 08 07 0D 0B 01 48 00 04 60 70 02 82 08 08 01 0E 04 0C 01 02 26 Rev. 0.0 HEX 80 08 07 0D 0C 01 48 00 04 60 70 02 82 04 04 01 0E 04 0C 01 02 26 Rev. 0.0 HEX 80 08 07 0D 0B 02 48 00 04 60 70 02 82 08 08 01 0E 04 0C 01 02 26 Rev. 0.0 HEX 80 08 07 0D 0C 02 48 00 04 60 70 02 82 04 04 01 0E 04 0C 01 02 26
Rev. 1.42, 2007-01 03292006-7CZA-YS85
27
Internet Data Sheet
HYS72D[64/128/256]xxx[G/H]BR-[5/6/7]-B Registered DDR SDRAM Module
HYS72D128300GBR-6-B
HYS72D128321GBR-6-B
HYS72D256320GBR-6-B
Organization
512MB x72 1 Rank (x8)
HYS72D64301GBR-6-B
Product Type
1 GByte x72 1 Rank (x4)
1 GByte x72 2 Ranks (x8)
2 GByte x72 2 Ranks (x4)
2 GByte x72 2 Ranks (x4)
Label Code JEDEC SPD Revision Byte# 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 - 40 41 42 43 44 45 46 47 48 - 61 62 63 Description Component Attributes tCK @ CLmax -0.5 (Byte 18) [ns] tAC SDRAM @ CLmax -0.5 [ns] tCK @ CLmax -1 (Byte 18) [ns] tAC SDRAM @ CLmax -1 [ns] tRPmin [ns] tRRDmin [ns] tRCDmin [ns] tRASmin [ns] Module Density per Rank tAS, tCS [ns] tAH, tCH [ns] tDS [ns] tDH [ns] Not used tRCmin [ns] tRFCmin [ns] tCKmax [ns] tDQSQmax [ns] tQHSmax [ns] not used DIMM PCB Height Not used SPD Revision Checksum of Byte 0-62
PC2700R PC2700R PC2700R PC2700R PC2700R -25331 -25330 -25330 -25330 -25331 Rev. 1.0 HEX C1 75 70 00 00 48 30 48 2A 80 75 75 45 45 00 3C 48 30 28 50 00 01 00 10 61 Rev. 0.0 HEX C1 75 70 00 00 48 30 48 2A 01 75 75 45 45 00 3C 48 30 28 50 00 00 00 00 CA Rev. 0.0 HEX C1 75 70 00 00 48 30 48 2A 80 75 75 45 45 00 3C 48 30 28 50 00 00 00 00 51 Rev. 0.0 HEX C1 75 70 00 00 48 30 48 2A 01 75 75 45 45 00 3C 48 30 28 50 00 00 00 00 CB Rev. 1.0 HEX C1 75 70 00 00 48 30 48 2A 01 75 75 45 45 00 3C 48 30 28 50 00 01 00 10 DC
Rev. 1.42, 2007-01 03292006-7CZA-YS85
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HYS72D256220GBR-6-B
Internet Data Sheet
HYS72D[64/128/256]xxx[G/H]BR-[5/6/7]-B Registered DDR SDRAM Module
HYS72D128300GBR-6-B
HYS72D128321GBR-6-B
HYS72D256320GBR-6-B
Organization
512MB x72 1 Rank (x8)
HYS72D64301GBR-6-B
Product Type
1 GByte x72 1 Rank (x4)
1 GByte x72 2 Ranks (x8)
2 GByte x72 2 Ranks (x4)
2 GByte x72 2 Ranks (x4)
Label Code JEDEC SPD Revision Byte# 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 Description Manufacturer's JEDEC ID Code (1) Manufacturer's JEDEC ID Code (2) Manufacturer's JEDEC ID Code (3) Manufacturer's JEDEC ID Code (4) Manufacturer's JEDEC ID Code (5) Manufacturer's JEDEC ID Code (6) Manufacturer's JEDEC ID Code (7) Manufacturer's JEDEC ID Code (8) Module Manufacturer Location Part Number, Char 1 Part Number, Char 2 Part Number, Char 3 Part Number, Char 4 Part Number, Char 5 Part Number, Char 6 Part Number, Char 7 Part Number, Char 8 Part Number, Char 9 Part Number, Char 10 Part Number, Char 11 Part Number, Char 12 Part Number, Char 13 Part Number, Char 14 Part Number, Char 15 Part Number, Char 16
PC2700R PC2700R PC2700R PC2700R PC2700R -25331 -25330 -25330 -25330 -25331 Rev. 1.0 HEX 7F 7F 7F 7F 7F 51 00 00 xx 37 32 44 36 34 33 30 31 47 42 52 36 42 20 20 20 Rev. 0.0 HEX 7F 7F 7F 7F 7F 51 00 00 xx 37 32 44 31 32 38 33 30 30 47 42 52 36 42 20 20 Rev. 0.0 HEX 7F 7F 7F 7F 7F 51 00 00 xx 37 32 44 31 32 38 33 32 31 47 42 52 36 42 20 20 Rev. 0.0 HEX 7F 7F 7F 7F 7F 51 00 00 xx 37 32 44 32 35 36 33 32 30 47 42 52 36 42 20 20 Rev. 1.0 HEX 7F 7F 7F 7F 7F 51 00 00 xx 37 32 44 32 35 36 32 32 30 47 42 52 36 42 20 20
Rev. 1.42, 2007-01 03292006-7CZA-YS85
29
HYS72D256220GBR-6-B
Internet Data Sheet
HYS72D[64/128/256]xxx[G/H]BR-[5/6/7]-B Registered DDR SDRAM Module
HYS72D128300GBR-6-B
HYS72D128321GBR-6-B
HYS72D256320GBR-6-B
Organization
512MB x72 1 Rank (x8)
HYS72D64301GBR-6-B
Product Type
1 GByte x72 1 Rank (x4)
1 GByte x72 2 Ranks (x8)
2 GByte x72 2 Ranks (x4)
2 GByte x72 2 Ranks (x4)
Label Code JEDEC SPD Revision Byte# 89 90 91 92 93 94 95 - 98 Description Part Number, Char 17 Part Number, Char 18 Module Revision Code Test Program Revision Code Module Manufacturing Date Year Module Manufacturing Date Week Module Serial Number
PC2700R PC2700R PC2700R PC2700R PC2700R -25331 -25330 -25330 -25330 -25331 Rev. 1.0 HEX 20 20 0x xx xx xx xx 00 Rev. 0.0 HEX 20 20 1x xx xx xx xx 00 Rev. 0.0 HEX 20 20 1x xx xx xx xx 00 Rev. 0.0 HEX 20 20 1x xx xx xx xx 00 Rev. 1.0 HEX 20 20 1x xx xx xx xx 00
99 - 127 Not used
Rev. 1.42, 2007-01 03292006-7CZA-YS85
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HYS72D256220GBR-6-B
Internet Data Sheet
HYS72D[64/128/256]xxx[G/H]BR-[5/6/7]-B Registered DDR SDRAM Module
TABLE 18
HYS72D[128/256]xxxGBR-7-B
HYS72D128300GBR-7-B HYS72D128321GBR-7-B HYS72D256220GBR-7-B Product Type HYS72D256320GBR-7-B 2 GByte x72 PC2100R- 20330 Rev. 0.0 HEX 80 08 07 0D 0C 02 48 00 04 70 75 02 82 04 04 01 0E 04 0C 01 02 26 C1
Organization
1 GByte x72 1 Rank (x4)
1 GByte x72
2 GByte x72
2 Ranks (x8) 2 Ranks (x4) 2 Ranks (x4) PC2100R- 20330 Rev. 0.0 HEX 80 08 07 0D 0B 02 48 00 04 70 75 02 82 08 08 01 0E 04 0C 01 02 26 C1 PC2100R- 20331 Rev. 1.0 HEX 80 08 07 0D 0C 02 48 00 04 70 75 02 82 04 04 01 0E 04 0C 01 02 26 C1
Label Code JEDEC SPD Revision Byte# 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 Description Programmed SPD Bytes in E2PROM Total number of Bytes in E PROM Memory Type (DDR = 07h) Number of Row Addresses Number of Column Addresses Number of DIMM Ranks Data Width (LSB) Data Width (MSB) Interface Voltage Levels tCK @ CLmax (Byte 18) [ns] tAC SDRAM @ CLmax (Byte 18) [ns] Error Correction Support Refresh Rate Primary SDRAM Width Error Checking SDRAM Width tCCD [cycles] Burst Length Supported Number of Banks on SDRAM Device CAS Latency CS Latency Write Latency DIMM Attributes Component Attributes
2
PC2100R- 20330 Rev. 0.0 HEX 80 08 07 0D 0C 01 48 00 04 70 75 02 82 04 04 01 0E 04 0C 01 02 26 C1
Rev. 1.42, 2007-01 03292006-7CZA-YS85
31
Internet Data Sheet
HYS72D[64/128/256]xxx[G/H]BR-[5/6/7]-B Registered DDR SDRAM Module
HYS72D128300GBR-7-B
HYS72D128321GBR-7-B
HYS72D256220GBR-7-B
Product Type
Organization
1 GByte x72 1 Rank (x4)
1 GByte x72
2 GByte x72
2 GByte x72
2 Ranks (x8) 2 Ranks (x4) 2 Ranks (x4) PC2100R- 20330 Rev. 0.0 HEX 75 75 00 00 50 3C 50 2D 80 90 90 50 50 00 41 4B 30 32 75 00 00 00 00 0D 7F PC2100R- 20331 Rev. 1.0 HEX 75 75 00 00 50 3C 50 2D 01 90 90 50 50 00 41 4B 30 32 75 00 01 00 10 98 7F PC2100R- 20330 Rev. 0.0 HEX 75 75 00 00 50 3C 50 2D 01 90 90 50 50 00 41 4B 30 32 75 00 00 00 00 87 7F
Label Code JEDEC SPD Revision Byte# 23 24 25 26 27 28 29 30 31 32 33 34 35 36 - 40 41 42 43 44 45 46 47 48 - 61 62 63 64 Description tCK @ CLmax -0.5 (Byte 18) [ns] tAC SDRAM @ CLmax -0.5 [ns] tCK @ CLmax -1 (Byte 18) [ns] tAC SDRAM @ CLmax -1 [ns] tRPmin [ns] tRRDmin [ns] tRCDmin [ns] tRASmin [ns] Module Density per Rank tAS, tCS [ns] tAH, tCH [ns] tDS [ns] tDH [ns] Not used tRCmin [ns] tRFCmin [ns] tCKmax [ns] tDQSQmax [ns] tQHSmax [ns] not used DIMM PCB Height Not used SPD Revision Checksum of Byte 0-62 Manufacturer's JEDEC ID Code (1)
PC2100R- 20330 Rev. 0.0 HEX 75 75 00 00 50 3C 50 2D 01 90 90 50 50 00 41 4B 30 32 75 00 00 00 00 86 7F
Rev. 1.42, 2007-01 03292006-7CZA-YS85
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HYS72D256320GBR-7-B
Internet Data Sheet
HYS72D[64/128/256]xxx[G/H]BR-[5/6/7]-B Registered DDR SDRAM Module
HYS72D128300GBR-7-B
HYS72D128321GBR-7-B
HYS72D256220GBR-7-B
Product Type
Organization
1 GByte x72 1 Rank (x4)
1 GByte x72
2 GByte x72
2 GByte x72
2 Ranks (x8) 2 Ranks (x4) 2 Ranks (x4) PC2100R- 20330 Rev. 0.0 HEX 7F 7F 7F 7F 51 00 00 xx 37 32 44 31 32 38 33 32 31 47 42 52 37 42 20 20 20 PC2100R- 20331 Rev. 1.0 HEX 7F 7F 7F 7F 51 00 00 xx 37 32 44 32 35 36 32 32 30 47 42 52 37 42 20 20 20 PC2100R- 20330 Rev. 0.0 HEX 7F 7F 7F 7F 51 00 00 xx 37 32 44 32 35 36 33 32 30 47 42 52 37 42 20 20 20
Label Code JEDEC SPD Revision Byte# 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 Description Manufacturer's JEDEC ID Code (2) Manufacturer's JEDEC ID Code (3) Manufacturer's JEDEC ID Code (4) Manufacturer's JEDEC ID Code (5) Manufacturer's JEDEC ID Code (6) Manufacturer's JEDEC ID Code (7) Manufacturer's JEDEC ID Code (8) Module Manufacturer Location Part Number, Char 1 Part Number, Char 2 Part Number, Char 3 Part Number, Char 4 Part Number, Char 5 Part Number, Char 6 Part Number, Char 7 Part Number, Char 8 Part Number, Char 9 Part Number, Char 10 Part Number, Char 11 Part Number, Char 12 Part Number, Char 13 Part Number, Char 14 Part Number, Char 15 Part Number, Char 16 Part Number, Char 17
PC2100R- 20330 Rev. 0.0 HEX 7F 7F 7F 7F 51 00 00 xx 37 32 44 31 32 38 33 30 30 47 42 52 37 42 20 20 20
Rev. 1.42, 2007-01 03292006-7CZA-YS85
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HYS72D256320GBR-7-B
Internet Data Sheet
HYS72D[64/128/256]xxx[G/H]BR-[5/6/7]-B Registered DDR SDRAM Module
HYS72D128300GBR-7-B
HYS72D128321GBR-7-B
HYS72D256220GBR-7-B
Product Type
Organization
1 GByte x72 1 Rank (x4)
1 GByte x72
2 GByte x72
2 GByte x72
2 Ranks (x8) 2 Ranks (x4) 2 Ranks (x4) PC2100R- 20330 Rev. 0.0 HEX 20 1x xx xx xx xx 00 PC2100R- 20331 Rev. 1.0 HEX 20 1x xx xx xx xx 00 PC2100R- 20330 Rev. 0.0 HEX 20 1x xx xx xx xx 00
Label Code JEDEC SPD Revision Byte# 90 91 92 93 94 95 - 98 Description Part Number, Char 18 Module Revision Code Test Program Revision Code Module Manufacturing Date Year Module Manufacturing Date Week Module Serial Number
PC2100R- 20330 Rev. 0.0 HEX 20 1x xx xx xx xx 00
99 - 127 Not used
Rev. 1.42, 2007-01 03292006-7CZA-YS85
34
HYS72D256320GBR-7-B
Internet Data Sheet
HYS72D[64/128/256]xxx[G/H]BR-[5/6/7]-B Registered DDR SDRAM Module
TABLE 19
HYS72D[128/256]xxxHBR-5-B
HYS72D128300HBR-5-B HYS72D128321HBR-5-B HYS72D256220HBR-5-B HYS72D64301HBR-5-B Product Type HYS72D256320HBR-5-B 2 GByte x72 2 Ranks (x4) Rev. 1.0 HEX 80 08 07 0D 0C 02 48 00 04 50 50 02 82 04 04 01 0E 04 1C 01 02 26
Organization
512MB x72 1 Rank (x8)
1 GByte x72 1 Rank (x4)
1 GByte x72 2 Ranks (x8)
2 GByte x72 2 Ranks (x4)
Label Code JEDEC SPD Revision Byte# 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 Description Programmed SPD Bytes in E PROM Total number of Bytes in E PROM Memory Type (DDR = 07h) Number of Row Addresses Number of Column Addresses Number of DIMM Ranks Data Width (LSB) Data Width (MSB) Interface Voltage Levels tCK @ CLmax (Byte 18) [ns] tAC SDRAM @ CLmax (Byte 18) [ns] Error Correction Support Refresh Rate Primary SDRAM Width Error Checking SDRAM Width tCCD [cycles] Burst Length Supported Number of Banks on SDRAM Device CAS Latency CS Latency Write Latency DIMM Attributes
2 2
PC3200R PC3200R PC3200R PC3200R PC3200R -30331 -30331 -30331 -30331 -30331 Rev. 1.0 HEX 80 08 07 0D 0B 01 48 00 04 50 50 02 82 08 08 01 0E 04 1C 01 02 26 Rev. 1.0 HEX 80 08 07 0D 0C 01 48 00 04 50 50 02 82 04 04 01 0E 04 1C 01 02 26 Rev. 1.0 HEX 80 08 07 0D 0B 02 48 00 04 50 50 02 82 08 08 01 0E 04 1C 01 02 26 Rev. 1.0 HEX 80 08 07 0D 0C 02 48 00 04 50 50 02 82 04 04 01 0E 04 1C 01 02 26
Rev. 1.42, 2007-01 03292006-7CZA-YS85
35
Internet Data Sheet
HYS72D[64/128/256]xxx[G/H]BR-[5/6/7]-B Registered DDR SDRAM Module
HYS72D128300HBR-5-B
HYS72D128321HBR-5-B
HYS72D256220HBR-5-B
Organization
512MB x72 1 Rank (x8)
HYS72D64301HBR-5-B
Product Type
1 GByte x72 1 Rank (x4)
1 GByte x72 2 Ranks (x8)
2 GByte x72 2 Ranks (x4)
2 GByte x72 2 Ranks (x4)
Label Code JEDEC SPD Revision Byte# 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 - 40 41 42 43 44 45 46 47 48 - 61 62 63 Description Component Attributes tCK @ CLmax -0.5 (Byte 18) [ns] tAC SDRAM @ CLmax -0.5 [ns] tCK @ CLmax -1 (Byte 18) [ns] tAC SDRAM @ CLmax -1 [ns] tRPmin [ns] tRRDmin [ns] tRCDmin [ns] tRASmin [ns] Module Density per Rank tAS, tCS [ns] tAH, tCH [ns] tDS [ns] tDH [ns] Not used tRCmin [ns] tRFCmin [ns] tCKmax [ns] tDQSQmax [ns] tQHSmax [ns] not used DIMM PCB Height Not used SPD Revision Checksum of Byte 0-62
PC3200R PC3200R PC3200R PC3200R PC3200R -30331 -30331 -30331 -30331 -30331 Rev. 1.0 HEX C1 60 50 75 50 3C 28 3C 28 80 60 60 40 40 00 37 41 28 28 50 00 01 00 10 67 Rev. 1.0 HEX C1 60 50 75 50 3C 28 3C 28 01 60 60 40 40 00 37 41 28 28 50 00 01 00 10 E1 Rev. 1.0 HEX C1 60 50 75 50 3C 28 3C 28 80 60 60 40 40 00 37 41 28 28 50 00 01 00 10 68 Rev. 1.0 HEX C1 60 50 75 50 3C 28 3C 28 01 60 60 40 40 00 37 41 28 28 50 00 01 00 10 E2 Rev. 1.0 HEX C1 60 50 75 50 3C 28 3C 28 01 60 60 40 40 00 37 41 28 28 50 00 01 00 10 E2
Rev. 1.42, 2007-01 03292006-7CZA-YS85
36
HYS72D256320HBR-5-B
Internet Data Sheet
HYS72D[64/128/256]xxx[G/H]BR-[5/6/7]-B Registered DDR SDRAM Module
HYS72D128300HBR-5-B
HYS72D128321HBR-5-B
HYS72D256220HBR-5-B
Organization
512MB x72 1 Rank (x8)
HYS72D64301HBR-5-B
Product Type
1 GByte x72 1 Rank (x4)
1 GByte x72 2 Ranks (x8)
2 GByte x72 2 Ranks (x4)
2 GByte x72 2 Ranks (x4)
Label Code JEDEC SPD Revision Byte# 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 Description Manufacturer's JEDEC ID Code (1) Manufacturer's JEDEC ID Code (2) Manufacturer's JEDEC ID Code (3) Manufacturer's JEDEC ID Code (4) Manufacturer's JEDEC ID Code (5) Manufacturer's JEDEC ID Code (6) Manufacturer's JEDEC ID Code (7) Manufacturer's JEDEC ID Code (8) Module Manufacturer Location Part Number, Char 1 Part Number, Char 2 Part Number, Char 3 Part Number, Char 4 Part Number, Char 5 Part Number, Char 6 Part Number, Char 7 Part Number, Char 8 Part Number, Char 9 Part Number, Char 10 Part Number, Char 11 Part Number, Char 12 Part Number, Char 13 Part Number, Char 14 Part Number, Char 15 Part Number, Char 16
PC3200R PC3200R PC3200R PC3200R PC3200R -30331 -30331 -30331 -30331 -30331 Rev. 1.0 HEX 7F 7F 7F 7F 7F 51 00 00 xx 37 32 44 36 34 33 30 31 48 42 52 35 42 20 20 20 Rev. 1.0 HEX 7F 7F 7F 7F 7F 51 00 00 xx 37 32 44 31 32 38 33 30 30 48 42 52 35 42 20 20 Rev. 1.0 HEX 7F 7F 7F 7F 7F 51 00 00 xx 37 32 44 31 32 38 33 32 31 48 42 52 35 42 20 20 Rev. 1.0 HEX 7F 7F 7F 7F 7F 51 00 00 xx 37 32 44 32 35 36 32 32 30 48 42 52 35 42 20 20 Rev. 1.0 HEX 7F 7F 7F 7F 7F 51 00 00 xx 37 32 44 32 35 36 33 32 30 48 42 52 35 42 20 20
Rev. 1.42, 2007-01 03292006-7CZA-YS85
37
HYS72D256320HBR-5-B
Internet Data Sheet
HYS72D[64/128/256]xxx[G/H]BR-[5/6/7]-B Registered DDR SDRAM Module
HYS72D128300HBR-5-B
HYS72D128321HBR-5-B
HYS72D256220HBR-5-B
Organization
512MB x72 1 Rank (x8)
HYS72D64301HBR-5-B
Product Type
1 GByte x72 1 Rank (x4)
1 GByte x72 2 Ranks (x8)
2 GByte x72 2 Ranks (x4)
2 GByte x72 2 Ranks (x4)
Label Code JEDEC SPD Revision Byte# 89 90 91 92 93 94 95 - 98 Description Part Number, Char 17 Part Number, Char 18 Module Revision Code Test Program Revision Code Module Manufacturing Date Year Module Manufacturing Date Week Module Serial Number
PC3200R PC3200R PC3200R PC3200R PC3200R -30331 -30331 -30331 -30331 -30331 Rev. 1.0 HEX 20 20 1x xx xx xx xx 00 Rev. 1.0 HEX 20 20 1x xx xx xx xx 00 Rev. 1.0 HEX 20 20 1x xx xx xx xx 00 Rev. 1.0 HEX 20 20 1x xx xx xx xx 00 Rev. 1.0 HEX 20 20 1x xx xx xx xx 00
99 - 127 Not used
Rev. 1.42, 2007-01 03292006-7CZA-YS85
38
HYS72D256320HBR-5-B
Internet Data Sheet
HYS72D[64/128/256]xxx[G/H]BR-[5/6/7]-B Registered DDR SDRAM Module
TABLE 20
HYS72D[128/256]xxxHBR-6-B
HYS72D128300HBR-6-B HYS72D128321HBR-6-B HYS72D256220HBR-6-B HYS72D64301HBR-6-B Product Type HYS72D256320HBR-6-B 2 GByte x72 2 Ranks (x4) Rev. 0.0 HEX 80 08 07 0D 0C 02 48 00 04 60 70 02 82 04 04 01 0E 04 0C 01 02 26
Organization
512MB x72 1 Rank (x8)
1 GByte x72 1 Rank (x4)
1 GByte x72 2 Ranks (x8)
2 GByte x72 2 Ranks (x4)
Label Code JEDEC SPD Revision Byte# 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 Description Programmed SPD Bytes in E PROM Total number of Bytes in E PROM Memory Type (DDR = 07h) Number of Row Addresses Number of Column Addresses Number of DIMM Ranks Data Width (LSB) Data Width (MSB) Interface Voltage Levels tCK @ CLmax (Byte 18) [ns] tAC SDRAM @ CLmax (Byte 18) [ns] Error Correction Support Refresh Rate Primary SDRAM Width Error Checking SDRAM Width tCCD [cycles] Burst Length Supported Number of Banks on SDRAM Device CAS Latency CS Latency Write Latency DIMM Attributes
2 2
PC2700R PC2700R PC2700R PC2700R PC2700R -25331 -25330 -25330 -25331 -25330 Rev. 1.0 HEX 80 08 07 0D 0B 01 48 00 04 60 70 02 82 08 08 01 0E 04 0C 01 02 26 Rev. 0.0 HEX 80 08 07 0D 0C 01 48 00 04 60 70 02 82 04 04 01 0E 04 0C 01 02 26 Rev. 0.0 HEX 80 08 07 0D 0B 02 48 00 04 60 70 02 82 08 08 01 0E 04 0C 01 02 26 Rev. 1.0 HEX 80 08 07 0D 0C 02 48 00 04 60 70 02 82 04 04 01 0E 04 0C 01 02 26
Rev. 1.42, 2007-01 03292006-7CZA-YS85
39
Internet Data Sheet
HYS72D[64/128/256]xxx[G/H]BR-[5/6/7]-B Registered DDR SDRAM Module
HYS72D128300HBR-6-B
HYS72D128321HBR-6-B
HYS72D256220HBR-6-B
Organization
512MB x72 1 Rank (x8)
HYS72D64301HBR-6-B
Product Type
1 GByte x72 1 Rank (x4)
1 GByte x72 2 Ranks (x8)
2 GByte x72 2 Ranks (x4)
2 GByte x72 2 Ranks (x4)
Label Code JEDEC SPD Revision Byte# 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 - 40 41 42 43 44 45 46 47 48 - 61 62 63 Description Component Attributes tCK @ CLmax -0.5 (Byte 18) [ns] tAC SDRAM @ CLmax -0.5 [ns] tCK @ CLmax -1 (Byte 18) [ns] tAC SDRAM @ CLmax -1 [ns] tRPmin [ns] tRRDmin [ns] tRCDmin [ns] tRASmin [ns] Module Density per Rank tAS, tCS [ns] tAH, tCH [ns] tDS [ns] tDH [ns] Not used tRCmin [ns] tRFCmin [ns] tCKmax [ns] tDQSQmax [ns] tQHSmax [ns] not used DIMM PCB Height Not used SPD Revision Checksum of Byte 0-62
PC2700R PC2700R PC2700R PC2700R PC2700R -25331 -25330 -25330 -25331 -25330 Rev. 1.0 HEX C1 75 70 00 00 48 30 48 2A 80 75 75 45 45 00 3C 48 30 28 50 00 01 00 10 61 Rev. 0.0 HEX C1 75 70 00 00 48 30 48 2A 01 75 75 45 45 00 3C 48 30 28 50 00 00 00 00 CA Rev. 0.0 HEX C1 75 70 00 00 48 30 48 2A 80 75 75 45 45 00 3C 48 30 28 50 00 00 00 00 51 Rev. 1.0 HEX C1 75 70 00 00 48 30 48 2A 01 75 75 45 45 00 3C 48 30 28 50 00 01 00 10 DC Rev. 0.0 HEX C1 75 70 00 00 48 30 48 2A 01 75 75 45 45 00 3C 48 30 28 50 00 00 00 00 CB
Rev. 1.42, 2007-01 03292006-7CZA-YS85
40
HYS72D256320HBR-6-B
Internet Data Sheet
HYS72D[64/128/256]xxx[G/H]BR-[5/6/7]-B Registered DDR SDRAM Module
HYS72D128300HBR-6-B
HYS72D128321HBR-6-B
HYS72D256220HBR-6-B
Organization
512MB x72 1 Rank (x8)
HYS72D64301HBR-6-B
Product Type
1 GByte x72 1 Rank (x4)
1 GByte x72 2 Ranks (x8)
2 GByte x72 2 Ranks (x4)
2 GByte x72 2 Ranks (x4)
Label Code JEDEC SPD Revision Byte# 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 Description Manufacturer's JEDEC ID Code (1) Manufacturer's JEDEC ID Code (2) Manufacturer's JEDEC ID Code (3) Manufacturer's JEDEC ID Code (4) Manufacturer's JEDEC ID Code (5) Manufacturer's JEDEC ID Code (6) Manufacturer's JEDEC ID Code (7) Manufacturer's JEDEC ID Code (8) Module Manufacturer Location Part Number, Char 1 Part Number, Char 2 Part Number, Char 3 Part Number, Char 4 Part Number, Char 5 Part Number, Char 6 Part Number, Char 7 Part Number, Char 8 Part Number, Char 9 Part Number, Char 10 Part Number, Char 11 Part Number, Char 12 Part Number, Char 13 Part Number, Char 14 Part Number, Char 15 Part Number, Char 16
PC2700R PC2700R PC2700R PC2700R PC2700R -25331 -25330 -25330 -25331 -25330 Rev. 1.0 HEX 7F 7F 7F 7F 7F 51 00 00 xx 37 32 44 36 34 33 30 31 48 42 52 36 42 20 20 20 Rev. 0.0 HEX 7F 7F 7F 7F 7F 51 00 00 xx 37 32 44 31 32 38 33 30 30 48 42 52 36 42 20 20 Rev. 0.0 HEX 7F 7F 7F 7F 7F 51 00 00 xx 37 32 44 31 32 38 33 32 31 48 42 52 36 42 20 20 Rev. 1.0 HEX 7F 7F 7F 7F 7F 51 00 00 xx 37 32 44 32 35 36 32 32 30 48 42 52 36 42 20 20 Rev. 0.0 HEX 7F 7F 7F 7F 7F 51 00 00 xx 37 32 44 32 35 36 33 32 30 48 42 52 36 42 20 20
Rev. 1.42, 2007-01 03292006-7CZA-YS85
41
HYS72D256320HBR-6-B
Internet Data Sheet
HYS72D[64/128/256]xxx[G/H]BR-[5/6/7]-B Registered DDR SDRAM Module
HYS72D128300HBR-6-B
HYS72D128321HBR-6-B
HYS72D256220HBR-6-B
Organization
512MB x72 1 Rank (x8)
HYS72D64301HBR-6-B
Product Type
1 GByte x72 1 Rank (x4)
1 GByte x72 2 Ranks (x8)
2 GByte x72 2 Ranks (x4)
2 GByte x72 2 Ranks (x4)
Label Code JEDEC SPD Revision Byte# 89 90 91 92 93 94 95 - 98 Description Part Number, Char 17 Part Number, Char 18 Module Revision Code Test Program Revision Code Module Manufacturing Date Year Module Manufacturing Date Week Module Serial Number
PC2700R PC2700R PC2700R PC2700R PC2700R -25331 -25330 -25330 -25331 -25330 Rev. 1.0 HEX 20 20 1x xx xx xx xx 00 Rev. 0.0 HEX 20 20 1x xx xx xx xx 00 Rev. 0.0 HEX 20 20 1x xx xx xx xx 00 Rev. 1.0 HEX 20 20 1x xx xx xx xx 00 Rev. 0.0 HEX 20 20 1x xx xx xx xx 00
99 - 127 Not used
Rev. 1.42, 2007-01 03292006-7CZA-YS85
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HYS72D256320HBR-6-B
Internet Data Sheet
HYS72D[64/128/256]xxx[G/H]BR-[5/6/7]-B Registered DDR SDRAM Module
TABLE 21
HYS72D[128/256]xxxHBR-7-B
HYS72D128300HBR-7-B HYS72D128321HBR-7-B HYS72D256220HBR-7-B Product Type HYS72D256320HBR-7-B 2 GByte x72 PC2100R- 20330 Rev. 0.0 HEX 80 08 07 0D 0C 02 48 00 04 70 75 02 82 04 04 01 0E 04 0C 01 02 26 C1
Organization
1 GByte x72 1 Rank (x4)
1 GByte x72
2 GByte x72
2 Ranks (x8) 2 Ranks (x4) 2 Ranks (x4) PC2100R- 20330 Rev. 0.0 HEX 80 08 07 0D 0B 02 48 00 04 70 75 02 82 08 08 01 0E 04 0C 01 02 26 C1 PC2100R- 20331 Rev. 1.0 HEX 80 08 07 0D 0C 02 48 00 04 70 75 02 82 04 04 01 0E 04 0C 01 02 26 C1
Label Code JEDEC SPD Revision Byte# 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 Description Programmed SPD Bytes in E PROM Total number of Bytes in E PROM Memory Type (DDR = 07h) Number of Row Addresses Number of Column Addresses Number of DIMM Ranks Data Width (LSB) Data Width (MSB) Interface Voltage Levels tCK @ CLmax (Byte 18) [ns] tAC SDRAM @ CLmax (Byte 18) [ns] Error Correction Support Refresh Rate Primary SDRAM Width Error Checking SDRAM Width tCCD [cycles] Burst Length Supported Number of Banks on SDRAM Device CAS Latency CS Latency Write Latency DIMM Attributes Component Attributes
2 2
PC2100R- 20330 Rev. 0.0 HEX 80 08 07 0D 0C 01 48 00 04 70 75 02 82 04 04 01 0E 04 0C 01 02 26 C1
Rev. 1.42, 2007-01 03292006-7CZA-YS85
43
Internet Data Sheet
HYS72D[64/128/256]xxx[G/H]BR-[5/6/7]-B Registered DDR SDRAM Module
HYS72D128300HBR-7-B
HYS72D128321HBR-7-B
HYS72D256220HBR-7-B
Product Type
Organization
1 GByte x72 1 Rank (x4)
1 GByte x72
2 GByte x72
2 GByte x72
2 Ranks (x8) 2 Ranks (x4) 2 Ranks (x4) PC2100R- 20330 Rev. 0.0 HEX 75 75 00 00 50 3C 50 2D 80 90 90 50 50 00 41 4B 30 32 75 00 00 00 00 0D 7F 7F PC2100R- 20331 Rev. 1.0 HEX 75 75 00 00 50 3C 50 2D 01 90 90 50 50 00 41 4B 30 32 75 00 01 00 10 98 7F 7F PC2100R- 20330 Rev. 0.0 HEX 75 75 00 00 50 3C 50 2D 01 90 90 50 50 00 41 4B 30 32 75 00 00 00 00 87 7F 7F
Label Code JEDEC SPD Revision Byte# 23 24 25 26 27 28 29 30 31 32 33 34 35 36 - 40 41 42 43 44 45 46 47 48 - 61 62 63 64 65 Description tCK @ CLmax -0.5 (Byte 18) [ns] tAC SDRAM @ CLmax -0.5 [ns] tCK @ CLmax -1 (Byte 18) [ns] tAC SDRAM @ CLmax -1 [ns] tRPmin [ns] tRRDmin [ns] tRCDmin [ns] tRASmin [ns] Module Density per Rank tAS, tCS [ns] tAH, tCH [ns] tDS [ns] tDH [ns] Not used tRCmin [ns] tRFCmin [ns] tCKmax [ns] tDQSQmax [ns] tQHSmax [ns] not used DIMM PCB Height Not used SPD Revision Checksum of Byte 0-62 Manufacturer's JEDEC ID Code (1) Manufacturer's JEDEC ID Code (2)
PC2100R- 20330 Rev. 0.0 HEX 75 75 00 00 50 3C 50 2D 01 90 90 50 50 00 41 4B 30 32 75 00 00 00 00 86 7F 7F
Rev. 1.42, 2007-01 03292006-7CZA-YS85
44
HYS72D256320HBR-7-B
Internet Data Sheet
HYS72D[64/128/256]xxx[G/H]BR-[5/6/7]-B Registered DDR SDRAM Module
HYS72D128300HBR-7-B
HYS72D128321HBR-7-B
HYS72D256220HBR-7-B
Product Type
Organization
1 GByte x72 1 Rank (x4)
1 GByte x72
2 GByte x72
2 GByte x72
2 Ranks (x8) 2 Ranks (x4) 2 Ranks (x4) PC2100R- 20330 Rev. 0.0 HEX 7F 7F 7F 51 00 00 xx 37 32 44 31 32 38 33 32 31 48 42 52 37 42 20 20 20 20 1x PC2100R- 20331 Rev. 1.0 HEX 7F 7F 7F 51 00 00 xx 37 32 44 32 35 36 32 32 30 48 42 52 37 42 20 20 20 20 1x PC2100R- 20330 Rev. 0.0 HEX 7F 7F 7F 51 00 00 xx 37 32 44 32 35 36 33 32 30 48 42 52 37 42 20 20 20 20 1x
Label Code JEDEC SPD Revision Byte# 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 Description Manufacturer's JEDEC ID Code (3) Manufacturer's JEDEC ID Code (4) Manufacturer's JEDEC ID Code (5) Manufacturer's JEDEC ID Code (6) Manufacturer's JEDEC ID Code (7) Manufacturer's JEDEC ID Code (8) Module Manufacturer Location Part Number, Char 1 Part Number, Char 2 Part Number, Char 3 Part Number, Char 4 Part Number, Char 5 Part Number, Char 6 Part Number, Char 7 Part Number, Char 8 Part Number, Char 9 Part Number, Char 10 Part Number, Char 11 Part Number, Char 12 Part Number, Char 13 Part Number, Char 14 Part Number, Char 15 Part Number, Char 16 Part Number, Char 17 Part Number, Char 18 Module Revision Code
PC2100R- 20330 Rev. 0.0 HEX 7F 7F 7F 51 00 00 xx 37 32 44 31 32 38 33 30 30 48 42 52 37 42 20 20 20 20 1x
Rev. 1.42, 2007-01 03292006-7CZA-YS85
45
HYS72D256320HBR-7-B
Internet Data Sheet
HYS72D[64/128/256]xxx[G/H]BR-[5/6/7]-B Registered DDR SDRAM Module
HYS72D128300HBR-7-B
HYS72D128321HBR-7-B
HYS72D256220HBR-7-B
Product Type
Organization
1 GByte x72 1 Rank (x4)
1 GByte x72
2 GByte x72
2 GByte x72
2 Ranks (x8) 2 Ranks (x4) 2 Ranks (x4) PC2100R- 20330 Rev. 0.0 HEX xx xx xx xx 00 PC2100R- 20331 Rev. 1.0 HEX xx xx xx xx 00 PC2100R- 20330 Rev. 0.0 HEX xx xx xx xx 00
Label Code JEDEC SPD Revision Byte# 92 93 94 95 - 98 Description Test Program Revision Code Module Manufacturing Date Year Module Manufacturing Date Week Module Serial Number
PC2100R- 20330 Rev. 0.0 HEX xx xx xx xx 00
99 - 127 Not used
Rev. 1.42, 2007-01 03292006-7CZA-YS85
46
HYS72D256320HBR-7-B
Internet Data Sheet
5
Package Outline
HYS72D[64/128/256]xxx[G/H]BR-[5/6/7]-B Registered DDR SDRAM Module
FIGURE 2
Package Outline Raw Card C - L-DIM-184-22-2
0.1 A B C
133.35 128.95
0.15 A B C 4 MAX.
A
4 0.1 28.58 0.13
1 2.5 0.1
o0.1 A B C
6.62 2.175 6.35
92
BC 0.4 1.27 0.1
64.77 95 x 1.27 = 120.65
49.53
3.8 0.13
1.8 0.1 93
0.1 A B C 184
10 17.8
3 MIN.
Detail of contacts
0.2
1.27
1 0.05
2.5 0.2
0.1 A B C
Burr max. 0.4 allowed
Notes 1. Drawing according to ISO 8015 2. Dimensions in mm 3. General tolerances +/- 0.15
Rev. 1.42, 2007-01 03292006-7CZA-YS85
47
Internet Data Sheet
HYS72D[64/128/256]xxx[G/H]BR-[5/6/7]-B Registered DDR SDRAM Module
FIGURE 3
Package Outline Raw Card B - L-DIM-184-23-2
0.1 A B C
133.35 128.95 4 MAX. A
0.15 A B C
4 0.1
1 2.5 0.1
o0.1 A B C
6.62 2.175 6.35
92
28.58 0.13
B 0.4 1.27 0.1 49.53 95 x 1.27 = 120.65 C 64.77 1.8 0.1 93 0.1 A B C 184
3.8 0.13
10
3 MIN.
Detail of contacts
0.2
1.27
1 0.05
2.5 0.2
0.1 A B C
Burr max. 0.4 allowed
Notes 1. Drawing according to ISO 8015 2. Dimensions in mm 3. General tolerances +/- 0.15
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48
17.8
Internet Data Sheet
HYS72D[64/128/256]xxx[G/H]BR-[5/6/7]-B Registered DDR SDRAM Module
FIGURE 4
Package Outline Raw Card F - L-DIM-184-25
0.1 A B C
133.35 128.95 4 MAX. A
0.15 A B C
4 0.1
1 2.5 0.1
92 o0.1 A B C 6.62 2.175 6.35 64.77 49.53
30.48 0.13
B 0.4 1.27 0.1 C 1.8 0.1 93 0.1 A B C 184
3.8 0.13
10
3 MIN.
Detail of contacts
0.2
1.27
1 0.05
2.5 0.2
0.1 A B C
Burr max. 0.4 allowed
Notes 1. Drawing according to ISO 8015 2. Dimensions in mm 3. General tolerances +/- 0.15
L-DIM-184-25
Rev. 1.42, 2007-01 03292006-7CZA-YS85
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17.8
Internet Data Sheet
HYS72D[64/128/256]xxx[G/H]BR-[5/6/7]-B Registered DDR SDRAM Module
Table of Contents
1 1.1 1.2 2 3 3.1 4 5 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 SPD Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Package Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Table of Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Rev. 1.42, 2007-01 03292006-7CZA-YS85
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Internet Data Sheet
Edition 2007-01 Published by Qimonda AG Gustav-Heinemann-Ring 212 D-81739 Munchen, Germany (c) Qimonda AG 2007. All Rights Reserved. Legal Disclaimer The information given in this Internet Data Sheet shall in no event be regarded as a guarantee of conditions or characteristics ("Beschaffenheitsgarantie"). With respect to any examples or hints given herein, any typical values stated herein and/or any information regarding the application of the device, Qimonda hereby disclaims any and all warranties and liabilities of any kind, including without limitation warranties of non-infringement of intellectual property rights of any third party. Information For further information on technology, delivery terms and conditions and prices please contact your nearest Qimonda Office. Warnings Due to technical requirements components may contain dangerous substances. For information on the types in question please contact your nearest Qimonda Office. Qimonda Components may only be used in life-support devices or systems with the express written approval of Qimonda, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system, or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may be endangered. www.qimonda.com

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